Books about MurogaMura Publications by Saburo Muroga [AKM 80] Alkhateeb, D., S. Kawasaki, and S. Muroga, "An Improvement
of a BranchandBound Algorithm for Designing NOR Optimal Networks,"
Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR801033,
Sept. 1980, 35 pp. [Ch 70] Chandersekaran, C. S., "Synthesis of Optimal DoubleRail Logic Networks Using NOROR Gates by Integer Programming," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Report No. 384, Feb. 1970. [Che 87] Chen, K. C., "Program PMIN for PLA minimization," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Aug. 1987, 153 pp. [CMFM 91] Chen, K.C., Y. Matsunaga, M. Fujita, and S. Muroga, "A resynthesis approach for network optimization," DA Conf., June 1721, 1991, San Franciso, pp. 458463. [C 90] Chen, K.C., "Logic Synthesis and Optimization Algorithms," PhD dissertation, Dept. of Comput. Sci., Univ. of Ill., Urbana, 1990, 320 pp. [CM 88] Chen, K.C. and S. Muroga, "Input Assignment Algorithm for DecodedPLA's with MultiInput Decoders," Int'l Conf. on CAD (ICCAD88), Nov. 710, 1988, pp. 474477. [CM 89a] Chen, K.C. and S. Muroga, "Sequential and Parallel Multipleoutput Ratioset Algorithms for the Speedup of PLA Minimization," CAD & CG '89, in Beijing, China, Aug. 1012, 1989, pp. 656662. [CM 89n] K.C. Chen and S. Muroga, "SYLONDREAM: A multilevel
network [CM 90] K.C. Chen and S. Muroga, "Timing optimization for multilevel combinational networks," Proc. 27th DAC '90, Florida, June 2527, 1990, pp. 339344. [Che 82] Cheng, B., "Minimal Parallel Binary Adders with AND/OR Gates and a Scheme for a Compact Parallel Multiplier,"Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, May 1982, 177 pp. [Cl 71] Culliney, J. N., "On the Synthesis by Integer Programming of Optimal NOR Gate Networks for Four Variable Switching Functions," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Report 480, Sept. 1971. [Cl 73] Culliney, J. N., "Use and Description of the CALCOMP Program to Draw Networks of Logic Gates," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR73580, June 1973. [Cl 75F] Culliney, J. N., "Program Manual: NOR Network Transduction Based on Connectable and Disconnectable Conditions (Reference Manual of NOR Network Transduction Programs NETTRAG1 and NETTRAG2)", Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR75698, Feb. 1975. [Cl 77] Culliney, J. N., "Topics in MOSFET Network Design," Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR77851, Feb. 1977. [CLK 74] Culliney, J. N., H. C. Lai, and Y. Kambayashi, "Pruning Procedures for NOR Networks Using Permissible Functions (Principles of NOR Network Transduction Programs NETTRAPG1, NETTRAP1 and NETTRAP2)," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR74690, Nov. 1974. [CM 76] Culliney, J. N., and S. Muroga, "A Study of Certain Factors Affecting Computation Times in Designing Optimal NOR Networks by the Implicit Enumeration Method Using the Feedforward Network Formulation,"Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR76807, June 1976. [CNM 76] Culliney, J. N., T. Nakagawa, and S. Muroga, "Results of the Synthesis of Optimal Networks of AND and OR Gates for FourVariable Switching Functions by a Branchandbound Computer Program," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR76789, March 1976. [CYNM 79] Culliney, J. N., M. H. Young, T. Nakagawa, and S. Muroga, "Results of the Synthesis of Optimal Networks of AND and OR Gates for FourVariable Switching Functions," IEEE TC, vol. C28, Jan. 1979, pp. 7685. [Ct 75] Cutler, R. B., "TISONSC1: A Program to Derive a Minimal Sum for a Switching Function," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, June 1975. [Ct 79] Cutler, R. B., "Program Manual for the Programs: ILLODMINSUMCBS, ILLODMINSUMCBSA, ILLODMINSUMCBG, and ILLODMINSUMCBGM to Derive Minimal Sums or Irredundant Disjunctive Forms for Switching Functions", Memo, Department of Computer Science, University of Illinois at UrbanaChampaign, 1979. [Ct 80] Cutler, R. B., "Algebraic Derivation of Minimal Sums for Functions of a Large Number of Variables," Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Apr. 1980. [CKM 79] Cutler, R. B., K. Kinoshita, and S. Muroga, "Exposition of Tison's Method to Derive All Prime Implicants and All Irredundant Disjunctive Forms for a Given Switching Function," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR79993, Oct. 1979, 128 pp. [CtM 79J] Cutler, R. B., and S. Muroga, "Comments on Generalization of Consensus Theory and Application to the Minimization of Boolean Function'", IEEE TC, vol. C28, July 1979, pp. 542543. [CtM 79N] Cutler, R. B., and S. Muroga, "Comments on 'Computing Irredundant Normal Forms for Abbreviated Presence Functions'," IEEE TC, vol. C28, Nov. 1979, pp. 874875. [CtM 80] Cutler, R. B., and S. Muroga, "Useless Prime Implicants of Incompletely Specified MultipleOutput Switching Functions," International J. Computer and Information Sciences, Aug. 1980, pp. 337350. [CtM 87] Cutler, R. B., and S. Muroga, "Derivation of Minimal Sums for Completely Specified Functions," IEEE TC, vol. C36, March 1987, pp. 277292. [CtM 90] Cutler, R. B., and S. Muroga, "Derivation of Minimal Sums
for MultipleOutput Functions," \fIIntl. Jour. Computer Aided VLSI
Design\fR, Vol. 2, No. 1, [Eda 85] Edamatsu, H., "Decomposition of Boolean Expressions Using Kernel," Memo, Dept of Computer Science, Univ. of Ill. at UrbanaChampaign, Aug. 1985, 51 pp. [Eda 85] Edamatsu, H., "A Program Manual of Decker," Memo, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Aug. 1985, 87 pp. [Fid 82] Fiduccia, N. S., "Logic Design of MOS Networks under Complexity Restrictions," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, May 1982. Also Rep. No. UIUCDCSR821100, July 1982, 129 pp. [Fuk 79] Fukushima, T., "Carry Propagation Delay in Minimum Parallel Binary Adders with NOR Gates," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, July 1979. Also, Rep. No. UIUCDCSR811058, March 1981, 103 pp. [Hh 75A] Hohulin, K. R., "Network Transduction Programs Based on Connectable and Disconnectable Conditions with FanIn and FanOut Restrictions (A description of NETTRAG1FIFO and NETTRAG2FIFO)," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR75719, April 1975. [Hh 75N] Hohulin, K. R., "A Code for Designing Optimal Networks by Implicit Enumeration Using the AllInterconnection Inequality Formulation (A Programming Manual for ILLODIEAIF)," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR75768, Nov. 1975. [HM 75] Hohulin, K. R., and S. Muroga, "Alternative Methods for Solving the CCTable in Gimpel's Algorithm for Synthesizing Optimal Three Level Nand Networks," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR75720, April 1975. [Hon 83] Hong, Sun Je, "Design of Minimal Programmable Logic Arrays," Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, July 1983, 314 pp. [Hon 83J] Hong, S. J., "User Manual for the Programs: ILLODAMIN, ILLODHMINS, ILLODHMINM to Derive Minimal Sums", Memo, Department of Computer Science, University of Illinois at UrbanaChampaign, 1983. [HonM 84] Hong, Sun Je, and S. Muroga, "Binary Logic Theory for Design of Minimal DecodedPLA's," Dept. of Computer Science, Univ. of Illinois at UrbanaChampaign, UIUCDCSR841192, Dec. 1984, 56 pp. [HonM 91] Hong, Sun Je, and S. Muroga, "Absolute Minimization of Completely Specified Functions," IEEE TC, vol. 40, No. 1, Jan. 1991, pp. 5365. [Hu 77Ja] Hu, J. K. C., "NOR (NAND) Network Design: ErrorCompensation Procedures for FanIn and FanOut Restricted Networks (NETTRAE1FIFO and NETTRAE2FIFO)," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR77847, Jan. 1977. [Hu 77Jb] Hu, J. K. C., "LevelRestricted NOR Network Transduction Procedures," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR77849, Jan. 1977. [Hu 77A] Hu, J. K. C., "Program Manual: For the NETTRA System," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR77887, Aug. 1977. [Hu 78] Hu, J. K. C., "Logic Design Methods for Irredundant MOS Networks," Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Aug. 1978. Also Rep. No. UIUCDCSR801053, 1980, 317 pp. [HM 77] Hu, J. K. C., and S. Muroga, "NOR Network Transduction
System [ILBM 69] Ibaraki, T., T. K. Liu, C. R. Baugh, and S. Muroga, "An Implicit Enumeration Program for ZeroOne Integer Programming," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Report No. 305, Jan. 1969. Also International J. of Computer and Information Sciences, Vol. 1, No. 1, March 1972, pp. 7592. [ILDM 71] Ibaraki, T., T. K. Liu, D. Djachan, and S. Muroga, "Synthesis of Optimal Networks with NOR and NAND Gates by Integer Programming," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Report No. 427, Jan. 1971. [IM 69] Ibaraki, T., and S. Muroga, "Synthesis of Networks with a Minimum Number of Negative Gates," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Report No. 309, Feb. 1969. Also IEEE TC, vol. C20, No. 1, Jan. 1971, pp. 4958. [IM 68] Ibaraki, T., and S. Muroga, "Adaptive linear classifier by integer programming", Dept. of Comp. Sci., Univ. of Illinois, Rep. 284, Sep. 27, 1968, 45 pp. [IM 68J] Ibaraki, T., and S. Muroga, "Implicit enumeration algorithm of integer programming on Illiac IV", Dept. of Comp. Sci., Univ. of Illinois, Rep. 319, Jan. 20, 1969, 29 pp. [IM 69F] Ibaraki, T., and S. Muroga, "Minimization of switching
networks using negative functions," Dept. of Comp. Sci., Univ. of
Illinois, Rep. 309, Feb. 17, 1969, 46 pp. [IF 79] Isoda, S., and E. FarzanKashani, "A Manual of SIMPL  A Logic Network Simulator for PLATO," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR79979, July 1979, 41 pp. [J 86] D. A. Jarosh, "DECOMPOSE: An Algorithm for PLA Decomposition", Master thesis, Dept. of Computer Science, University of Illinois at UrbanaChampaign, Aug. 1986, 113 pp. [Jha\ 86] Jha, M. K., "Program Manual for Programs: ILLODMINICBINC and ILLODMINICBAINC", Memo, Department of Computer Science, University of Illinois at UrbanaChampaign, 1986. [KC 76] Kambayashi, Y., Y., and J. N. Culliney, "NOR Network Transduction Procedures Based on Connectable and Disconnectable Conditions (Principles of NOR Network Transduction Programs NETTRAG1 and NETTRAG2)," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR76841, Dec. 1976. [KLCM 75] Kambayashi, Y., H. C. Lai, J. N. Culliney, and S. Muroga, "NOR Network Transduction Based on ErrorCompensation (Principles of NOR Network Transduction Programs NETTRAE1, NETTRAE2 and NETTRAE3)," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR75737, June 1975. [KLM 90] Kambayashi, Y., H. C. Lai, and S. Muroga, "Patternoriented transformations of NOR networks ," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR901573, UILUENG901711, Feb. 1990, 48pp. [KM 76] Kambayashi, Y., and S. Muroga, "Network Transduction Based on Permissible Functions (General Principles of NOR Network Transduction NETTRA Programs)," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR76804, June 1976. [KM 86] Kambayashi, Y. and S. Muroga, "Properties of Wired Logic," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR841183, Aug. 1984, 49 pp. Also IEEE TC, vol.C35, June 1986, pp.550563. [Kws 80] Kawasaki, S., "An Improvement of a BranchandBound Algorithm for Designing NOR Optimal Networks," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, July 1980. [Kw 74] Kawasaki, T., "Optimal Networks with NOROR Gates and WiredOR Logic," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Report No. 623, Jan. 1974. [Kr 85J] Krolikoski, S. J., "Program Manual for SQUEEZES and SQUEEZED," Memo, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Jan. 1985, 45 pp. [Kr 85M] Krolikoski, S. J., "The SQUEEZE Algorithm for PLA Minimization," Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, March 1985, 193 pp. [Ky 85] Kyu, G. Y., "Design of Minimal MOS Networks," Master thesis, Dept. of Electrical and Computer Engineering, Unv. of Ill. at UrbanaChampaign, Oct. 1985, 291 pp. [La 75] Lai, H. C., "Program Manual: NOR Network Transduction by Generalized Gate Merging and Substitution (Reference Manual of NOR Network Transduction Programs NETTRAG3 and NETTRAG4)," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR75714, April 1975. [La 76] Lai, H. C., "A Study of Current Logic Design Problems," Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Jan. 1976, 373 pp. [La 80] Lai, H. C., "Design of Diagnosable MOS Networks," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR79996, Dec. 1979, 172 pp. [LC 74] Lai, H. C., and J. N. Culliney, "Program Manual: NOR Network Pruning Procedures Using Permissible Functions (Reference Manual of NOR Network Transduction Programs NETTRAPG1, NETTRAP1, and NETTRAP2,)" Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR74686, Nov. 1974. [LC 75] Lai, H. C., and J. N. Culliney, "Program Manual: NOR Network Transduction Based on ErrorCompensation (Reference Manual of NOR Network Transduction Programs NETTRAE1, NETTRAE2 and NETTRAE3,)" Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR75732, June 1975. [LCM 90] Lai, H. C., J. N. Culliney and S. Muroga, "Design of Testable MOS Networks and Test Set Generation," in \fIAdvances in ComputerAided Engineering Design Vol. 2\fR, ed. by I. N. Hajj, 1990, pp. 235275, JAI Press Ltd, London. [LK 75] Lai, H. C., and Y. Kambayashi, "NOR Network Transduction by Generalized Gate Merging and Substitution Procedures (Principles of NOR Network Transduction Programs NETTRAG3 and NETTRAG4)," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR75728, June 1975. [LM 79] Lai, H. C., and S. Muroga, "Minimum Parallel Binary Adders with NOR (NAND) Gates," IEEE TC, vol. C28, Sept. 1979, pp. 648659. [LM 82] Lai, H. C., and S. Muroga, "Logic Networks of CarrySave Adders," IEEE TC, vol. C31, No. 9, Sept. 1982, pp. 870882. Also Rep. No. UIUCDCSR821080, Jan. 1982, 41 pp. [LM 85] Lai, H. C., and S. Muroga, "Automated Logic Design Of MOS Networks," Chapter 5 in the book, \fI"Advances In Information Systems Science\fR", vol. 9, edited by J. Tou, Plenum Press, 1985, pp. 287336. [LM 87] Lai, H. C. and S. Muroga, "Logic Networks with a Minimum Number of NOR (NAND) Gates for Parity Functions of n Variables," IEEE TC, vol. C36, No.2, Feb. 1987, pp. 157166. [LM 88] Lai, H. C. and S. Muroga, "Design of MOS networks in singlerail input logic for incompletely specified functions," IEEE TCAD, vol. 7, pp. 339345, March 1988. [LNM 74] Lai, H. C., T. Nakagawa, and S. Muroga, "Redundancy Check Technique for Designing Optimal Networks by BranchAndBound Method," International J. of Computer and Information Sciences, Sept. 1974, pp. 251271. [Leg 74] Legge, J. G., "The Design of NOR Networks under FanIn and FanOut Constraints (A Programming Manual for FIFOTRANG1))," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR74661, June 1974. (M.S. thesis, Department of Electrical Engineering.) [Lim 88] Limqueco, J. C., "Algorithms for the design of irredundant MOS networks", Master thesis, Dept. of Comput. Sci., University of Illinois, Urbana, IL, 87 pp. 87, 1988. [Lim 92] Limqueco, J. C., "Logic optimization of MOS networks", PhD thesis, Dept. of Comput. Sci., University of Illinois, Urbana, IL, 250 pp., 1992. [LM 90] Limqueco, J. C., and S. Muroga, "SYLONREDUCE: A MOS network optimization algorithm using permissible functions," ICCD '90, Cambridge, MA, Sept. 1719, 1990, pp. 282285. [LM 91Ju] Limqueco, J. C., and S. Muroga, "Logic optimization of MOS networks," DA Conf., June 1721, 1991, San Francisco, pp. 464469. [LM 91S] Limqueco, J. C., and S. Muroga, "Timing optimization of MOS combinational networks," 4th Intl. ASIC Conf., Sept. 2327, 1991, Rochester, NY, P134. [LM 92] Limqueco, J. C., and S. Muroga, "Optimizing large networks by repeated local optimization using a windowing scheme," Intl. Symp. on Circuits and Systems, May 1013, 1992, San Diego, CA, pp. 19931996. [Lin 88R] Lin, L.P., "Reference Manual of Fortran Program ILLOD(NORB)3 for Design of Optimal NOR Networks," Memo, Dept. of Computer Science, Univ. of Illinois, 95 pp., Sept. 1988. [Lin 88T] Lin, L.P., "Design of Optimal NOR Networks by an Extension of the BranchandBound Method and the Transduction Method," Master thesis, Dept. of Computer Science, Univ. of Illinois, 83 pp., Sept. 1988. [Li 68] Liu, T. K., "A Code for ZeroOne Integer Linear Programming by Implicit Enumeration (A Programming Manual for ILLIP)," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Report No. 302, Dec. 1968. [Li 72] Liu, T. K., "Synthesis of Logic Networks with MOS Complex Cells," Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Report No. 517, May 1972. [Li 75] Liu, T. K., "Synthesis Algorithms for 2Level MOS Networks," IEEE TC, vol. C24, No. 1, Jan. 1975, pp. 7279. [Li 77J] Liu, T. K., "Synthesis of Multilevel FeedForward MOS Networks," IEEE TC, vol. C26, June 1977, pp. 581588. [Li 77A] Liu, T. K., "Synthesis of FeedForward MOS Networks with Cells of Similar Complexities," IEEE TC, vol. C26, Aug. 1977, pp. 826831. [LHSM 74] Liu, T. K., K. Hohulin, L. E. Shiau, and S. Muroga, "Optimal OneBit Full Adders with Different Types of Gates," IEEE TC, vol. C23, Jan. 1974, pp. 6370. [LNM 70] Liu, T. K. T. Nakagawa, and S. Muroga, "Synthesis of Networks of MOS Cells by Integer Programming," Internal Memo, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, 1970, 36 pages. [MiM 85] Miyanaga, Y. and S. Muroga, "Design of nMOS Networks by Factorization," Memo, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Aug. 1985, 97 pp. [Mi 85] Miyanaga, Y., "A User's Manual of NEGFAC, a Program for Design of Negative Gate Networks by Factorization," Memo, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, 1985, 65 pp. [MT 72] MoraTovar, J. J., "A Study of the Effect of Additional Inequalities in Integer Programming for Logical Design," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Report No. 543, Oct. 1972. [M\ 70] Muroga, S., "Logical Design of Optimal Digital Networks by Integer Programming," Chapter 5 of book \fIAdvances in Information Systems Science\fR, vol. 3, edited by J. T. Tou, Plenum Press, 1970, pp. 283348. [M 71] Muroga, S., "\fIThreshold Logic and Its Applications\fR", John Wiley, 1971, 478 pages (now available from Krieger Publishing Company, Inc., Melbourne, Florida 329029542). [M\ 79] Muroga, S., "\fILogic Design and Switching Theory\fR", John Wiley, 1979, 617 pages. (now available from Krieger Publishing Company, Inc., Melbourne, Florida 329029542). Also Japanese translation, Kyoritsu Pub. Co., Tokyo, 1981. [M 82] Muroga, S., "\fIVLSI System Design\fR", John Wiley, 1982, 496 pages. (now available from Krieger Publishing Company, Inc., Melbourne, Florida 329029542). [M 85] Muroga, S., "Logic Design of VLSI Electronic Circuit  Tutorial,"
(Invited paper), 23 pp., at International Workshop on Parallel Computing
and VLSI, [M 87] Muroga, S., "Very Large Scale Integration Design", \fIEncyclopedia of Physical Science and Technology\fR, vol.14, pp. 306327, ed. by R. A. Meyers, Academic Press, 1987. [M 91] Muroga, S., "Computeraided logic synthesis for VLSI chips", \fIAdvances in Computers\fR, vol.32, pp. 1103, ed. by M. C. Yovits, Academic Press, San Diego, CA, 1991. [M 92] Muroga, S., "Logic synthesizers, the Transduction method
and its extension, SYLON", Intl. Symp. on Logic Synthesis and Microprocessor
Architecture, as a part of Intl. Symp. on Information Sciences, July 1215,
1992, at Kyushu Institute of [M 93] Muroga, S., "Logic synthesizers, the Transduction method
and its extension, SYLON", in the book, \fILogic Synthesis and Optimization\fR,
ed. by T. Sasao, Kluwer Academic Publishers, [M 94] Muroga, S., ``Computers'', Encyclopaedia Britannica, Macropaedia
[M 95a] Muroga, S., "Logic synthesizer for engineering changes", [M 95b] Muroga, S., "Comparison of engineering education in US and Japan", (in Japanese), The Institute of Electronics, Information and Communication Engineers, Dec. 1995, pp. 12051209. [M 00] Muroga, S., "Basic differences in university education in US and Japan", (in Japanese), The Institute of Electronics, Information and Communication Engineers, March 2000, pp. 163165. [M 02] Muroga, S., Editorial board for The Computer Engineering Handbook, ed. by V. G. Oklobdzija, CRC Press, 2002. [MI\ 68] Muroga, S., and T. Ibaraki, "Logical Design of an Optimum Network by Integer Programming," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Part 1, Report No. 264, July 1968; and Part 2, Report No. 289, Dec. 1968. [MI 72] Muroga, S., and T. Ibaraki, "Design of Optimal Switching
Networks by Integer Programming," IEEE TC, vol. C21, June 1972,
[MIK 76] Muroga, S., T. Ibaraki, and T. Kitahashi, [MKLC 89] S. Muroga, Y. Kambayashi, H. C. Lai and J. N. Culliney, "The
transduction methodDesign of logic networks based on permissible [ML\ 74] Muroga, S., and H. C. Lai, "Minimization of Logic [ML 76] Muroga, S., and H. C. Lai, "Minimization of Logic Networks
[MXLLC 89] S. Muroga, X.Q. Xiang, J. Limqueco, L.P. Lin, and K.C. Chen, [N 77] Nakagawa, T., "Reference Manual of FORTRAN Program [NL 71D] Nakagawa, T., and H. C. Lai, "Reference Manual of FORTRAN Program ILLOD(NORB) for Optimal NOR Networks," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Report No. 488, Dec. 1971. [NL 85] Nakagawa, T. T. and H. C. Lai, "Reference Manual of FORTRAN
[NLM 84] Nakagawa, T. T., H. C. Lai, and S. Muroga, "Design Algorithm of the Optimal NOR Networks by the Branchandbound Approach," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR841128, Dec. 1984, 36 pp. [NLM 89] Nakagawa, T. T., H. C. Lai, and S. Muroga, "Design Algorithm of Optimal Logic Networks by the BranchandBound Approach," \fIIntl. Jour. Computer Aided VLSI Design\fR, Vol. 1, No. 2, 1989, pp. 203231, Ablex Publishing Corp., Norwood, NJ. [NM 69] Nakagawa, T. and S. Muroga, "Exposition of Davidson's Thesis 'An Algorithm for NAND Decomposition of Combinational Switching Systems,'" Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSF71869, Aug. 1969. [NM 71] Nakagawa, T. and S. Muroga, "Comparison of the Implicit Enumeration Method and the BranchandBound Method for Logical Design," Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Report No. 455, June 1971. [Pl 74] Plangsiri, B., "NOR Network Transduction Procedures: "Merging of Gates," and "Substitution of Gates" for FanIn and FanOut Restricted Networks ETTRAG3FIFO and NETTRAPG1FIFO)," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR74688, Dec. 1974. [Sak\ 79] Sakurai, A., "Parallel Binary Adders with a Minimum Number of Connections," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Aug. 1979. [SM 83] Sakurai, A. and S. Muroga, "Parallel Binary Adders with a Minimum Number of Connections," IEEE TC, vol. C32, Oct. 1983, pp. 969976. [San 83] Sandell, T. E., "Manual for Program MAPVIEW," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, 69 pp. [SKM 92] Sawada, S., Y. Kambayashi, and S. Muroga, "Generation of fanin restricted initial networks for Transduction method", Proc. of Synthesis and Simulation Meeting and Intl. Interchange, SASIMI'92, April 68, 1992, Kobe, Japan, pp. 3645. [S 71] Shiau, L. E., "Design of Optimal OneBit Adder Networks by Integer Linear Programming," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Report No. 425, Jan. 1971. [SM 81] Shimizu, K. and S. Muroga, "Interactive Logic Design of MOS Networks," Preliminary Memo, Nov. 1981. [S 72] Shinozaki, T., "Computer Program for Designing Optimal Networks with MOS Gates," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Report No. 502, April 1972. [Su 81] Suga, M., "ComputerAided Design of Compact Electronic Circuits in TTL and ECL," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Aug. 1981, 159 pp. [Sw 70] Swee, R. S., "Optimum Network Design Using NOROR Gates by Integer Programming,"Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, Report No. 375, Feb. 1970. [We 77] Wei, A., "BranchandBound Approach and Other Alternative Methods for Solving the CCTable in Gimpel's Optimal TANT Network Design," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, May 1975. [Wo 82] Wong, K., "Interactive Design of MOS Circuits," Master thesis, Dept. of Elec. Eng., Univ. of Ill. at UrbanaChampaign, Sept. 1982. [Xi 84] Xiang, X. Q., "INTFOLD: An Interactive Program for Folding
Programmable Logic Arrays," Master thesis, Dept. of Computer Science,
[Xi 90] Xiang, X. Q., "Multilevel Logic Network Synthesis System, SYLONXTRANS, and ReadOnly Memory Minimization Procedure, MINROM," PhD dissertation, Dept. of Comput. Sci., Univ. of Illinois, Urbana, 1990, 286 pp. [XiM 86] Xiang, X. Q. and S. Muroga, "Interactive Reduction of Folded PLA," Proc. IEEE Intl. Conf. Comput. Design: VLSI in Computers, Oct. 69, 1986 at Port Chester, New York, (ICCD'86), pp. 592595. [XiM 89] X. Q. Xiang and S. Muroga, "Synthesis of multilevel networks with simple gates," International Workshop on Logic Synthesis, sponsored by the Microelectronics Center of North Carolina in cooperation with ACM SIGDA, held at Research Triangle Park, North Carolina, May 2326, 1989. (A summary was included in the proceedings by mistake instead of final paper.) [Xu 83] Xu, H. M., "User Manual for MINSUMC system," Memo,
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[YKM 95] Yamashita, S., Y. Kambayashi and S. Muroga, "Design of logic circuits with wiredlogic utilizing transduction method", (in Japanese) Transaction of the Institute of Electronics, Information, and Communication Engineers, DI, Vol. J79DI, No. 3, March 1996, pp. 132139. [YKM 96] Yamashita, S., Y. Kambayashi and S. Muroga, "Design of logic circuits with Wiredlogic utilizing Transduction method," Trans. Inst. Electronics, Information and Engineer, DI, Vol. J79DI, No. 3, March 1996, pp. 132139. [Ye\ 77] Yeh, CC., "Design of Irredundant MultipleLevel MOS Networks for MultipleOutput and Incompletely Specified Functions," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR77896, Sept. 1977. [Yo\ 77] Young, M. H., "An Implicit Enumeration Program for ZeroOne Integer ProgrammingILLIP2," Master thesis, Dept. of Computer Science, Univ. of Ill. at UrbanaChampaign, UIUCDCSR77884, June 1977. .ti 1.25i [Yo 79] Young, M. H., "The Minimal Covering Problem and Automated
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